Spiking Neural Network on Chip

Project Synopsis

This project aims to design and implement an efficient hardware for a multi-layered self-trainable spiking neural network for real-time pattern detection.

Project Details

This project focuses on designing and implementing an efficient hardware system for a multi-layered self-trainable spiking neural network that can detect patterns in streaming data. The primary application of this project is for intrusion detection in IoT or Autonomous systems. The project utilizes a supervised training algorithm named ODESA, which is the first network to have end-to-end multi-layer online local supervised training without using gradients. The algorithm combines the adaptation of weights and thresholds in an efficient hierarchical structure.

The implementation of the project consists of a multi-layer Spiking Neural Network (SNN) and individual training modules for each layer that enable online self-learning without using back-propagation. This approach utilizes simple local adaptive selection thresholds, a Winner-Takes-All (WTA) constraint on each layer, and a modified weight update rule that is more amenable to hardware. The trainer module allocates neuronal resources optimally at each layer, without having to pass high-precision error measurements across layers. All elements in the system, including the training module, interact using event-based binary spikes.

The hardware-optimized implementation of the project has shown to preserve the performance of the original algorithm across multiple spatial-temporal classification problems while significantly reducing hardware requirements. The project demonstrates that the network architecture and online training of weights and thresholds can be implemented efficiently on a large scale in hardware. This system has significant potential in detecting anomalies and intrusions in IoT and autonomous systems, making them more secure and reliable.

Project Publications

• Efficient Implementation of a Multi-Layer Gradient-Free Online-Trainable Spiking Neural Network on FPGA.
  Subject of DST disclosure approval. Application under review.

• An Optimized Multi-layer Spiking Neural Network implementation in FPGA Without Multipliers
  Accepted on INNS DLIA 2023